The present invention relates generally to integrated circuits, and in particular to electrostatic discharge (ESD) protection of circuitry coupled to an input stage of an integrated circuit.
The protection of integrated circuits (ICs) from damage due to ESD has received increased design attention, particularly as circuit geometries migrate to smaller dimensions. The book xe2x80x9cESD in Silicon Integrated Circuitsxe2x80x9d by A. Amerasekera and C. Duvvury, copyrighted in 1995 by John Wiley and Sons, which is hereby incorporated by reference, discloses many techniques for providing protection from electrostatic discharge phenomena. ESD damage can occur as a result of a voltage ESD event or a current ESD event. An ESD event may cause current of magnitudes in the range of one-half to three amperes. The damage may occur during manufacture of the IC chip, or more commonly, after the chip is packaged such as during handling, shipping or use.
One ESD protection technique to protect the input of a packaged IC employs resistors to reduce ESD currents transmitted through bond pads to circuits on the IC. ESD events are transmitted to chip bond pads of packaged chips by package leads. Another technique employs a transistor to clamp the operating voltage on an input bond pad to a safe level. Yet another technique employs a four-layer device, such as a thyristor, to introduce hysteresis into the protective circuitry.
Yet another technique for protecting the input of an integrated circuit from an ESD event has been to provide two steering diodes, each having an area large enough to conduct the expected current. In this technique as shown in FIG. 10, one steering diode, SD1, is coupled between the input bond pad and the positive voltage supply pad, VccP. Another steering diode SD2, is coupled between ground bond pad 18j and the input bond pad 16j, with its anode coupled to ground and its cathode coupled to the input bond pad. Under normal operating conditions, steering diodes SD1 and SD2 are reversed biased. A clamping device, such as a zener diode ZDj is coupled between the positive voltage supply bond pad VccP and the ground bond pad 18j. With its cathode coupled to VccP and its anode coupled to ground, diode ZDj under normal operation of the circuit of FIG. 10 is reversed biased and non-conducting. When the positive supply voltage exceeds a normal operating voltage, diode ZDj goes into avalanche breakdown and conducts. Subsequently, when the voltage at the positive supply voltage pad VccP decreases to normal operating levels, the zener diode ZDj turns off.
An ESD test is normally conducted on a package in which an integrated circuit chip is encapsulated without a supply voltage applied. With transistor 14j not coupled to the input 5 bond pad, a positive ESD pulse between the input bond pad and ground bond pad forward biases steering diode SD1.
During a negative ESD event when the voltage at the input bond pad of FIG. 10 is more negative than the ground bond pad, the steering diode SD2 becomes forward biased with a low voltage drop such that the transistor 14j, which concurrently is reverse biased, is not damaged.
During a positive ESD event, the reverse bias voltage across diode ZDj of FIG. 10 increases and diode ZDj goes into breakdown mode and conducts. The voltage at the positive voltage supply will rise until clamping device ZDj conducts. The voltage at the input pad will rise to the level of the breakdown voltage of diode ZDj plus the forward voltage drop of the steering diode. When the base of the transistor is connected to the input bond pad, the transistor will become forward biased. If the transistor is large enough, the transistor will carry all of the current caused by the ESD event to the ground bond pad without being damaged.
While such techniques have offered some ESD protection, further improvement is considered necessary. The need for enhanced limited current ESD event protection of circuits coupled to an input bond pad of an integrated circuit operable at radio frequencies of operation increase is desirable.
In accordance with the present invention, an integrated circuit includes an input bond pad and a ground bond pad. A circuit coupled between the input bond pad and the ground bond pad includes a transistor having a first electrode coupled to the input bond pad and a second electrode coupled to the ground bond pad. A steering diode is coupled between the input bond pad and the ground bond pad. The steering diode is reverse biased, both under normal operating conditions and during an ESD event, when a voltage applied to the input bond pad exceeds the voltage at the ground bond pad.
There may be other circuit elements between the emitter and the ground bond pad. At least two series connected diodes are coupled between the input bond pad and the ground bond pad. The anode of one of the at least two series connected diodes is coupled to the input bond pad. The cathode of one of the at least two series connected diodes is coupled to the ground bond pad. The at least two series connected diodes contribute, along with the steering diode, to ESD protection of the circuit coupled between the input bond pad and the ground bond pad.